Method and system for bonding a semiconductor chip onto a carrier using micro-pins

ABSTRACT

An anisotropically conductive layer “ACL” ( 50 ) for mechanical and electrical bonding of two circuit containing structures, such as a flip chip and carrier is disclosed. The ACL is formed of a rigid insulating substrate ( 72 ) or membrane ( 61 ) with a top and bottom planar surfaces formed with a plurality of pins therein. The pins extend beyond the top and bottom surfaces so that a portion of each pin is exposed. The pins provide electrical connection between contact terminals or pads of the flip chip and carrier and additionially provide mechanical support between the flip chip and carrier so that the flip chip can under go post-bonding processing without substantial deformation or breaking. A method of electrically and mechanically bonding the flip chip and carrier and a method of making a semiconductor device using the ACL is also disclosed.

RELATED APPLICATIONS

[0001] This application claims priority from U.S. Provisionalapplication 60/220,709 filed Jul. 26, 2000, which is herein incorporatedby reference.

BACKGROUND OF INVENTION

[0002] The invention relates to the field of semiconductor circuits anddevices packaging generally, and in particular, Active Packaging of thetype described in U.S. Pat. No. 5,496,743 incorporated herein byreference. Active Packaging relates to the bonding of a flip chip onto acarrier. For this purpose, a carrier is any electronic circuitcontaining structure, such as a wafer, a plate, a printed circuit boardor another chip and a flip chip is a circuit containing structure thatundergoes partial processing on one side, is then flipped and furtherprocessing is performed on the other side of the chip. In ActivePackaging, the partially processed flip chip is bonded onto the carrierbefore processing of the integrated circuit chip is complete. Thus, in atypical scenario, a semiconductor flip chip is partially processed onone side, bonded onto a carrier such that electrical and mechanicalconnections between the flip chip and carrier are accomplished, thenfinal processing on the other side of the flip chip occurs. Finalprocessing can include lithography, etching, layer deposition, doping,thinning and other processing steps well known to one of ordinary skillin the art. This technique is often used as a preferred alternative towire bonding two separate circuit containing parts.

[0003] Several methods other than wire bonding are known for bonding anintegrated circuit chip onto a carrier. One technique previouslyutilized was Z-axis conductive film adhesives. A typical example of thistechnique is illustrated in FIG. 1. There, flip chip 11, and carrier 15are electrically and mechanically connected using a Z-axis conductivefilm adhesive which consists of conductive particles 13 with diameter of5-100 μM (microns) contained in an adhesive resin 14. The resin 14,mechanically holds the carrier wafer 15 to the flip chip 11 and alsoinsulates the conductivc particles 13 from one another Conductiveparticles 13 mechanically interface with contact pads 12 on the flipchip 11 and carrier 15, thereby ensuring electrical connection betweenrespective contact pads 12 of the flip chip 11 and those of the carrier15.

[0004] This technique suffers from the disadvantage that the number ofconductive particles per contact pad is not large, which dictates thatlarge forces will have to be applied between flip chip 11 and carrier 15in order to ensure sufficient electrical contact between the respectivecontact pads 12. This relatively large force creates substantial stresson the flip chip after bonding, which makes the technique unsuitable forthe brittle and/or thin flip chips that are used in Active Packaging.Additionally, the differences in thermal expansion coefficients of athin flip chip and the adhesive resin or epoxy create further mechanicalstresses during thermal cycling. Further, in today's high densityintegrated circuits, the electrical contact pads are so closely spacedthat the conductive particles may be too large to ensure the contactpads are electrically isolated from each other. Finally, the need for anadhesive such as an epoxy or resin to provide mechanical bonding betweenthe flip chip and the carrier creates problems when the back of the flipchip must remain free from contamination so post-bonding processing mayoccur.

[0005] Another bonding technique known in the art is solder ball andepoxy encapsulation. This technique is illustrated in FIG. 2A. In thismethod solder balls 23 are bonded on electrical contact pads 22 of acarrier 25, and the contact pads 22 of the flip chip 21 are aligned withand soldered to respective ones of the solder balls 23. The size of thesolder ball is typically between 50 and 150 microns. Epoxy resin 24 isapplied after soldering to make a stable bonded structure. This methodof epoxy encapsulation suffers from the same disadvantages as the Z-axisadhesive film technique previously described.

[0006] In an effort to overcome the problems of contaminating the flipchip with epoxy or other resin, a revised solder ball epoxy bondingtechnique has been proposed, as illustrated in FIG. 2B. In this revisedtechnique, the adhesive layer 33 is pre-formed on the carrier 15.Moreover, the solder balls 31 are first soldered to the contact pads 14of the flip chip 11. The solder balls 31 are formed with a pointed endso that they may penetrate the adhesive layer 33 during the mountingprocess when pressure is applied between the flip chip 11 and thecarrier 15. The pointed solder balls are pressure bonded to respectiveelectrodes 32 of the chip carrier 15 without the adhesive film cominginto contact with the flip chip 11. Although this technique overcomesthe problem of contamination of the flip chip by the adhesive material,it still suffers from the other defects previously mentioned, includingthe presence of large mechanical stresses on the flip chip afterbonding.

[0007] A revised approach has been proposed to overcome some of thelimitations associated with prior bonding techniques. This approach,illustrated in FIG. 3, utilizes a Z-axis oriented multiple metal fibrilsor tubules 16 embedded in a soft porous membrane 17, such as liquidcrystal or a polymer. This technique is described in detail in U.S. Pat.Nos. 5,805,424, 5,805,425, 5,805,426 and 5,818,700, which areincorporated herein by reference. According to this technique, thediameter of the metal fibrils 16 and the distance between adjacentfibrils in the membrane is much smaller than the typical spacing betweenadjacent contact pads 18 on the flip chip 11 and the carrier 15, and thetypical contact pad size. In this manner, many metal fibrils are inelectrical contact with each contact pad 18 on the flip chip 11 andcarrier 15 so that the electrical contact resistance between opposingcontact pads 18 is much smaller than in the conventional Z-axisconductive film techniques. Bonding between the flip chip 11 and carrier15 is achieved by applying pressure to the thermo-compressible material.

SUMMARY OF THE INVENTION

[0008] It is an object of the present invention to provide an improvedmethod and system for electrical and mechanical bonding of two circuitcontaining elements such as a chip carrier and flip chip. This advantageis achieved by the use of an anisotropically conductive bondinginterface (referred to herein as an anisotropically conductive layer)which is composed of a rigid insulating substrate or membrane with topand bottom planar surfaces. A plurality of conductive rigid pins areembedded in the substrate, and each pin extends beyond the top andbottom planar surfaces, forming what might appear to be a “bed ofnails”. This arrangement provides for electrical conductivity throughthe pins in the direction normal to the planar surfaces, but not inother directions, since the pins are electrically isolated from oneanother. The pins are arranged so that when the anisotropicallyconductive layer is placed between two circuit containing structures,the electrical contact pads on each structure are contacted by aplurality of the pins. When the two circuit containing structures arebonded to one another, a plurality of pins will connect one contact padon the first circuit containing structure to an associated contact padon the other circuit containing structure. Moreover, those pinsextending beyond the planar surfaces of the conductive layer'sinsulating substrate that are not involved in the electrical connectionof respective electrical contact pads of the two circuit containingstructures act to provide mechanical support to one or both of thecircuit containing structures.

[0009] In an exemplary embodiment, the diameter of the portion of thepins that extends beyond the planar surfaces of the insulating substrateis substantially the same as the diameter of the portion of the pinsinside the substrate.

[0010] In another exemplary embodiment, the diameter of the portion ofthe pins that extends beyond the planar surfaces of the insulatingsubstrate may be enlarged compared to the diameter of the portion of thepins inside the substrate.

[0011] In a further preferred embodiment, the diameter of the pinsproviding mechanical, but not electrical contact are larger than thediameter of the pins providing electrical connection between contactpads.

[0012] In another preferred embodiment, the nominal diameter of the pinsis between 0.01 microns and 0.4 microns.

[0013] In another exemplary embodiment, the pins protrude from theplanar surfaces of the insulating substrate by an amount substantiallyequal to the distance the electrical contact pads protrude from thecircuit containing structure (i.e. the pad thickness).

[0014] In another exemplary embodiment, the pins protrude from theplanar surfaces of the insulating substrate by an amount that issubstantially the same as the distance between pins.

[0015] In yet another exemplary embodiment, the pins are substantiallyevenly distributed throughout the insulating substrate weith an averagedistance between neighboring pins. This distance may be equal to or lessthan the thickness of the flip chip (wvhich is bound to a carrier by theanisotropically conductive layer) after final processing.

[0016] In a still further exemplary embodiment, the distance between thetwo planar surfaces of the insulating substrate is between 5 and 25microns, and the substrate may be formed from SiC, SiNx, SiO₂, mica,polycarbonate or alumina (aluminum oxide), which may be formed byanodization of high purity (i.e. over 99.9% pure) aluminum foil.

[0017] In another exemplary embodiment, the anisotropic conducting layeris bonded onto the circuit containing structures by soldering some ofthe pins onto the electrical contact pads of the circuit containingstructure. In a further exemplary embodiment, the anisotropic conductinglayer is bonded onto the circuit containing structures by physicallypenetrating some of the pins into the electrical contact pads of thecircuit containing structure by respective pins making electricalcontact to the pads and without soldering. For this purpose, it may beadvantageous to form the contact pads from a material that is softerthan the material from which the pins are formed. For example, if thepins were formed of copper, the contact pads may be formed from Sn, Pb,In or alloys thereof.

[0018] In a still further exemplary embodiment, a soft insulatingmaterial is applied either to the whole surface of one of the circuitcontaining structures (including the contact pads), or to those portionsof the circuit containing structure that are not electrical contactpads. The anisotropic conducting layer is then bonded onto the circuitcontaining structure by penetrating respective pins into the electricalcontact pads and the soft insulating material.

[0019] In a final exemplary embodiment, a semiconductor device, such asa high-speed heterojunction bipolar transistor is manufactured byperforming a series of processing steps on a semiconductor substrate topartially fabricate a semiconductor device, bonding thepartially-fabricated semiconductor substrate to a carrier chip in a flipchip fashion using an anisotropic conducting layer of the typepreviously described, and performing a series of final processing stepson the bonded partially-fabricated semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 shows the cross-sectional view of a prior art technique forbonding a chip onto a carrier using conductive particles and an adhesiveresin

[0021]FIG. 2A shows the cross-sectional view of a prior art techniquefor bonding a chip onto a carrier using solder balls and an epoxy.

[0022]FIG. 2B shows the cross-sectional view of a modified version ofthe technique illustrated in FIG. 2A.

[0023]FIG. 3 shows the cross-sectional view of a prior art technique forbonding a flip chip to a carrier using a soft Z-axis conductive filmwith embedded conductive tubules.

[0024] FIGS. 4A-4F show the cross-sectional view of an exemplarytechnique for forming an anisotropically conductive layer in accordancewith the present invention.

[0025] FIGS. 5A-5F show the cross-sectional view of another exemplarytechnique for forming an anisotropically conductive layer in accordancewith the present invention.

[0026] FIGS. 6A-6F show the cross-sectional view of another exemplarytechnique for forming an anisotropically conductive layer in accordancewith the present invention.

[0027] FIGS. 7A-7B show the cross-sectional view of an exemplarytechnique for bonding a circuit containing structure to ananisotropically conductive layer in accordance with the presentinvention.

[0028] FIGS. 8A-8B show the cross-sectional view of another exemplarytechnique for bonding a circuit containing structure to ananisotropically conductive layer in accordance with the presentinvention.

[0029]FIG. 9 shows the cross-sectional view of a partially processedsemiconductor device suitable for bonding as a flip chip (shown beforeit is flipped for further processing) in an exemplary embodiment of thepresent invention.

[0030]FIG. 10 shows the cross-sectional view of a circuit containingstructure suitable for use as a carrier in an exemplary embodiment ofthe present invention.

[0031]FIG. 11 shows the cross-sectional view of an anisotropicallyconductive layer disposed above a carrier wafer before bonding on acarrier in an exemplary embodiment of the present invention.

[0032]FIG. 12 shows the cross-sectional view of a partially processedsemiconductor device chip bonded in a flip chip fashion (shown afterflipping) to a carrier using an anisotropically conductive layer in anexemplary embodiment of the present invention.

[0033]FIG. 13 shows the cross-sectional view of a fully processedsemiconductor device chip bonded to a carrier using an anisotropicallyconductive layer in accordance with an exemplary embodiment of thepresent invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0034] Referring to FIGS. 4A-4F, the steps involved in an exemplarymethod of forming an anisotropically conductive layer 50 of the presentinvention are illustrated. The illustrated steps involve the use of thenuclear track-etch method, which is well known to one of ordinary skillin the art. The pin diameter 58, or pin hole diameter 57, obtained bythis method can range from 0.01 microns to a few tens of microns. Thedistribution of hole diameters is sharp, with deviations from the rateddiameter of typically less than 20%. Preferably, the hole diametersrange from 0.01 micron to about 0.5 micron. Porous membranes prepared bythis method can be purchased commercially, or prepared as describedbelow. The commercial product can be obtained from Corning (Nucleporemembranes) or from Osmonics (Poretics Policarbonate Track-Etch (PCTE)membranes). If a commercial product is employed, pins must be formed inthe porous material using, for example, the electroplating techniquediscussed herein.

[0035] The process begins with a three membrane layers 51, 52, 53. Inthe exemplary embodiment, the layers consist of 10 microns of mica 52,sandwiched between two layers of 2.5 micron thick polycarbonate 51, 53.The thickness of the outer layers 51, 53 are preferably proportional tothe diameter of the pin holes formed using this method, with smallerdiameter pins corresponding to thinner outer layers 51, 53, so as tomaintain mechanical rigidity of the anisotropically conductive layer.Outer layers 51, 53 should be capable of being removed, such as by aselective etch method, without damaging the integrity of the middlesubstrate layer 52 or the pins 58.

[0036] Vertically oriented tracks 56 are then formed in the three layermembrane by bombarding the membrane with charged accelerated nuclearfission particles from a radioactive source, such as radioactiveCalifornium or by placing the membrane into a nuclear reactor. Thenumber of tracks per unit area depends primarily on the exposure timeand the flux of energetic nuclear particles. By varying theseparameters, it is possible to control the average density of resultingtracks. Once the energized particles have created randomly distributedtracks 56 with sufficient density (although the tracks are shown withregular spacing in FIGS. 4B-4C, in practice the spacing between tracks56 will vary), which constitute normally-oriented damaged regions in themembrane layers 51, 52, 53, the membrane layers are exposed to ananisotropic etchant such that the etch rate for damaged regions isfaster than the etch rate for undamaged regions. In the exemplaryembodiment, two or three etch and rinse steps are employed using twodifferent etchants, the different steps corresponding to the outer andinner layers of the three membrane layers 51, 52, 53. In this manner,holes are formed along each of the tracks extending completely throughthe membrane layers 51, 52, 53. For example, the tracks in outerpolycarbonate layers 51, 53 may be etched with NaOH, which does notsubstantially etch the mica layer 52. The nuclear tracks in the micalayer 52 (which is mainly composed of SiO₂) may be etched with asolution of hydrofluoric acid HF.

[0037] Once holes have been formed in the three membrane layers 51, 52,53 one of the outside layers 53 is coated with metal layer 54. The metallayer, in turn, is mounted on conductive substrate 55. Any metal withgood conductance, such as copper or gold, will suffice for theconductive substrate 55. Alternatively, the conductive substrate 55 canbe made of a soft metal, such as Indium, and the three layer membranecan be pressed against that metal. In this case it may be unnecessary tocover the outer membrane layer 53 with metal layer 54.

[0038] In FIG. 4D, metal pins 58 are formed in the previously formedholes 57 using traditional electroplating of the metal layer 54 in eachof the holes 57. The metal chosen should have a melting temperaturehigher than the relevant soldering temperature, such as 500° C. so thepins 58 will maintain their shape during any subsequent soldering.Moreover, the metal should be sufficiently hard so as to not deformduring the bonding of a flip chip onto a carrier. In the preferredembodiment, copper is chosen for the metal pins 58.

[0039] After pin formation, the membrane layers 51, 52, 53 and pins 58are demounted from backside metal 54 and substrate 55. This can beachieved by mechanically separating the membrane from the substrate 55,using, for example, a sharp blade. The connection between the substrate55 and the membrane 51, 52, 53 is typically not strong, as themechanical connection consists primarily of the pin cross-sections thatwere grown from the metal substrate 55 up into the hole 57.

[0040] After the demounting step, the top and bottom membrane layers 51,53 are removed by an etchant that selectively removes polycarbonatelayers 51 and 53, while leaving the middle layer 52 and metal pins 58intact, resulting in the anisotropically conductive layer shown in FIG.4E. An alkaline solution of NaOH may be used for this purpose. As shownin FIG. 4F, an optional further step of electroplating (such aselectroless plating), can be conducted to make the diameter of theexposed portion 59 of each of the metal pins 58 larger than theunexposed portion, thus preventing the metal pins from becoming movablein the vertical direction in the rigid insulating membrane, alsoreferred to as substrate 52. The resulting anisotropically conductivelayer 50, may then be used to electrically and mechanically bond twocircuit containing structures.

[0041] In a similar exemplary embodiment (not shown), a single materialmembrane may be used, for example a polycarbonate layer a few micronsthick. The process proceeds much like the three-layer techniquedescribed, i.e. formation of nuclear track-generated holes and fillingof these holes with metal by electroplating. At the end of this process,the outer portions of each pin are exposed by partial etching of themembrane in a chemical that removes the membrane material but does notdamage the pin material. An alkaline solution of NaOH is suitable forthis purpose.

[0042] The pins 58 of the anisotropically conductive layer 50 must, onaverage, be spaced sufficiently close so as to keep the circuitcontaining structure, such as the flip chip, that they support fromdeforming caused by mechanical forces exerted on the chip by the pins58. For example, a flip chip may encounter mechanical forces duringbonding with another circuit containing substrate such as a carrierwafer or chip, or during subsequent processing steps such as thinning.The forces encountered by the flip chip may be approximated bytraditional stress and strain equations well known to one of ordinaryskill in the art and are more easily understood with reference to a thinsquare plate with side lengths L (corresponding to the average distancebetween pins) and thickness t. If the plate is supported only at itsfour corners and a pressure P is applied to the plate, the maximumdeformation (i.e. bending of the plate) is: $\begin{matrix}{{B_{\max} = {{- \alpha}\frac{{PL}^{4}}{{Et}^{3}}}},} & \left( {{Eq}.\quad 1} \right)\end{matrix}$

[0043] where a is a geometrical factor (0.0444 for a square plate) and Eis Young's modulus of elasticity (131 GPa in the <100> direction forsilicon).

[0044] Using the formula in Eq. 1, it can be shown that for a pressuresP of approximately 10 atm (or 10⁶ Pa, which is larger than the pressuresencountered during most processing operations such as bonding andthinning), a plate thickness t of five microns, and plate length L ofone micron, the maximum deformation of the plate is approximately 3×10⁻⁹microns, which is negligible and should not result in fracturing of theplate. Similarly, assuming the material to be a polyamide (a materialtypically used to form an insulation layer in semiconductor devices)rather than silicon, the maximum deformation increases to the order of10⁻⁴ microns, which again is negligible and should not result infracturing of the plate. However, if the length L is increased to tenmicrons, the maximum deformation increases to approximately 0.35 micronsand 3.5 microns for Silicon and polyamide respectively, which issufficient to fracture the plate. Consequently, to ensure the flip chipdoes not fracture, the distance L between unsupported portions of theflip chip should remain at approximately 1 micron or less. This impliesthat the distance between adjacent pins 58 in the anisotropicallyconductive layer 50 should be approximately 1 micron or less.

[0045] Notably, if the pin distance is 1 micron and the total chip sizeis approximately 1×1 mm², there will be approximately one million pins58 supporting the chip. Accordingly, the 10 atm pressure P applied tothe flip chip during processing will be spread over all the pins 58,resulting in a force of about 10⁻⁶ N on each pin, which is sufficientlysmall to prevent pin deformation, assuming a pin diameter ofapproximately 0.5 microns.

[0046] Referring now to FIGS. 5A-5E, an alternative approach toconstructing an anisotropically conductive layer using an anodic aluminamembrane is illustrated. The porous membranes can be either prepared asdescribed below, or purchased from, for example, Fisher Scientific(Whatman Anodisc filter membranes with pore diameters from 0.02 micronto 0.2 micron). Porous oxide growth on very pure aluminum under anodicbias in various electrolytes has been well known in the art for a numberof years. A description of the process appears in U.S. Pat. No.6,045,677, incorporated herein by reference. Porous membranes formed inthis matter are characterized by narrow vertical pores with sharp porediameter distribution and overall uniformity of pores throughout themembrane surface. More recently it was found that for a narrow range ofgrowth parameters, it is possible to obtain a self-organized denselypacked hexagonal pore structure. See H. Masuda et al., Appl. Phys. Lett.vol. 71, p. 2270-72 (1997), incorporated herein by reference.

[0047] High purity aluminum foil 61 (more than 99.9% pure) withthickness of a few microns, is mounted on a conductive metal plate 62,such as a copper plate. Regularly distributed holes 63 are formed in themembrane 61 by slow anodization in 0.3 M oxalic acid solution, at 15-17degrees C., under a constant voltage of 40 V, as described in H. Masudaand K. Fukuda, Science vol. 268, p.1466-68 (1995), incorporated hereinby reference. The diameters of holes 63 can be further adjusted bydipping of the anodized porous membrane into various acidic solutions.Preferred acids include sulfiric, phosphoric and oxalic acids. Hole sizeusing this technique can vary from 0.01 microns to 0.4 microns.Typically, a lower layer of the aluminum foil 61 remains in the metallicstate, and the holes in the anodized alumina terminate without going allthe way through, as shown in FIG. 5C. After anodization, the aluminumsubstrate and the bottom part of the porous layer can be etched awaywith saturated HgCl₂.

[0048] Holes 63 are then ready for filling with metal. In an exemplaryembodiment, the holes 63 are filled with metal to make pins 64 using ACelectroplating of the metal plate 62 in each of the holes 64, or usingelectroless electroplating, which are well known to one of ordinaryskill in the art. See R. M. Metzger et. al., IEEE Trans. on Magnetics,vol. 36, p. 30 (2000). Both methods allow for filling the incompletehole 63 with metal despite the fact that there is a thin partition ofinsulating alumina between the interior of the hole 63 and the metalsubstrate 62. Regular electroplating can be used if the bottom part ofthe membrane has been etched with HgCl₂ and the holes have been openedon both ends.

[0049] Once the pins 64 are formed, the membrane and pins aremechanically demounted from the conductive substrate 62. Etching in anappropriate acid or other chemical, such as saturated HgCl₂ whichremoves alumina but not the metal pins, is then performed to removeresidual Aluminum from the membrane and to thin the alumina membrane soas to expose the top and bottom portions of the pins, resulting in thestructure shown in FIG. 5D. Again, it is possible to use electroless orother standard plating techniques to increase the diameter of theexposed portions of the pins 64 as a final processing step. Theresulting anisotropically conductive layer 60 is shown in FIG. 5E.

[0050] Referring now to FIGS. 6A-6F, a third approach to constructing ananisotropically conductive layer is presented using a traditionalphotolithography and etching technique. An approximately 40 to 100micron thick insulating membrane 72, such as Silicon is formed on aconductive substrate 73. A photoresist layer 71 is applied to coat thetop surface of the membrane 72 as illustrated in FIG. 6A. The insulatingmembrane 72 may be a carbon doped silicon material, mica, or quartzplatelet. The photoresist may be any general negative photo resist suchas AZ-5200, manufactured by AZ Electronic Materials of Somerville, N.J.The closely spaced hole array pattern 74 is then exposed in thephotoresist using a suitable mask. To ensure the holes are spacedclosely enough, it is preferred to employ optical lithography using UVlight or electron beam lithography. After the exposed photoresist 71 isdeveloped to form the photoresist pattern shown in FIG. 6B, the membrane72 masked by the photoresist pattern is subjected to a highlyanisotropic etchant, such as induction coupled plasma (ICP) etching. Ifmembrane 72 is composed of SiO₂, the plasma may consist mainly of CF₄;if the membrane 72 is composed of SiC, it may consist mainly of SF₆. TheICP technique is known to produce high aspect ratio vertical holes 75through the membrane, as shown in FIG. 6C. The holes 75 are filled withmetal by electroplating the metal substrate 73 through the holes 75, asshown in FIG. 6D. The membrane with metal filled holes 76 is thendemounted from substrate 73. The photoresist layer 71 is then removedand further etching takes place to expose the top and bottom portion ofthe pins 76, forming the structure shown in FIG. 6E. Electroless orregular electroplating may then be employed to increase the diameter ofthe exposed portion 77 of the pins 76, forming the anisotropicallyconductive layer 70, as shown in FIG. 6F.

[0051] The anisotropically conductive layer of the present invention 50,60, 70 may be used to electrically and mechanically bond two circuitcontaining structures, such as a flip chip and chip carrier. FIGS. 7A-7Billustrate an exemplary method of bonding an anisotropically conductivelayer 50, 60, 70 to a circuit containing structure 81. The structure 81has electrical contact pads 82, which protrude from its surface. Thebonding of the anisotropically conductive layer 50, 60, 70 to thestructure 81 is achieved by soldering respective pluralities of themetal pins 94 with the contact pads 82, or by mechanically penetratingthe contact pads 82 with respective pluralities of the metal pins 94 ofanisotropically conductive layer 50, 60, 70, as shown in FIG. 7A. Thepins not soldered to or penetrating the contact pads 82, contact thesurface of structure 81, providing mechanical support to the structure81. Consequently, the length of the exposed portion of the pins in theanisotropically conductive layer 50, 60, 70 is comparable to or greaterthan the distance the electrical contact pads 82 extend from the surfaceof structure 81 (i.e. the pad thickness).

[0052] Referring now to FIGS. 8A-8B, another exemplary method of bondingthe anisotropically conductive layer 50, 60, 70 onto circuit containingstructure 91 is illustrated. In this embodiment, a soft insulatingmaterial is applied to coat the surface of structure 91, but not to coatthe surface of electrical contact pads 93. The thickness of the softinsulating layer 92 should be approximately the same as the distance theelectrical contact pads 93 protrude from the surface of structure 91.The bonding of the anisotropically conductive layer 50, 60, 70 to thestructure 91 is achieved by soldering respective pluralities of themetal pins 94 to the contact pads 93, or by mechanically penetrating thecontact pads 93 with the metal pins of anisotropically conductive layer50, 60, 70. The pins not bonded to the electrical contact pads 93penetrate the soft insulating material 92, forming mechanical bonds thathelp to distribute forces applied to the anisotropically conductivelayer over the bonded surface of the structure 91. Altematively,(although not shown in FIG. 8A), the soft insulating material may coverthe entire surface of structure 91. In that case, the pins wouldpenetrate the soft insulator material both to make electrical contact tothe pads and to make mechanical contact to the rest of the surface ofthe structure.

[0053] Referring now to FIGS. 9-13, an exemplary embodiment of a methodfor manufacturing a semiconductor device, such as a heterojuntionbipolar transistor (HBT) 130 using the anisotropically conductive layer50, 60, 70 of the present invention is illustrated. FIG. 9 illustrates apartially processed HBT chip 100. The partially processed HBT chip 100consists of InP substrate 109 and five epitaxially grown layersincluding a 100 nm thick n+ type InGaAs emitter contact layer 103, an ntype InP emitter layer 104, a p+ type InGaAs base layer 106, an n-typeInGaAs subcollector layer 107 and an n+ type InGaAs collector layer 108.The emitter layer 104 and the emitter contact layer 103, are etched toform a mesa shape. A Si₃N₄ passivation layer 1010 is then formed on thebase layer 106 and the mesa layers 103 and 104 using PECVD. The Si₃N₄layer 1010 is then etched to make openings for ohmic contact electrodelayers 105 and 1011 for the base and emitter, respectively, which areformed by conventional metallization, photolithography and etching. Thesurface of the chip 100 is then covered with a layer of insulatormaterial 101, such as a polyamide. Holes are then formed in the layer ofinsulating material 101 from the top surface to each of the base andemitter ohmic contact electrodes 105 and 1011, using photolithographyand anisotropic plasma etching. Electrical contact terminals or pads 102are formed on the base and emitter ohmic contact electrodes 105 and 1011using electroplating.

[0054]FIG. 10 illustrates an electronic circuit containing structure orcarrier, 110, having conventional electronic circuits (e.g., integratedcircuits) contained in semiconductor layer 116. The semiconductor layer116 is covered by a layer of Si₃N₄, which has openings for contactelectrodes 113 to the electronic circuits in the layer 116. A furtherlayer 112, preferably of a polyamide, is formed over the Si₃N₄ layer 115and the contact electrodes 113. Holes are formed in the layer 112extending from its top surface to respective contact electrodes 113 byconventional photolithography and anisotropic etching, the holes arefilled with metal and a contact pad 111 is formed over each hole byelectroplating of the contact electrode through each of the holes. Inthis manner, electrical contact terminals or pads 111 are provided atthe surface of layer 112 for electrical connection to the electroniccircuits contained in the semiconductor layer 116.

[0055]FIG. 11 illustrates the anisotropically conductive layer 50, 60,70 positioned above the carrier 110 just before bonding thereon. Thebonding technique may be any of the methods previously described withreference to FIGS. 7A-7B, 8A-8B. As can be seen, proper alignmentbetween the structure 110 and the anisotropically conductive layer isnot necessary as long as electrical contact terminals 111 are in contactwith an adequate number of pins of the anisotropically conductive layer50, 60, 70; however, to ensure maximum mechanical support of the carrierand/or the flip chip, the anisotropically conductive layer 50, 60, 70should include a sufficient number of pins to cover as much of theinterface surface of carrier 110 as possible.

[0056] Referring now to FIGS. 9 and 12, the electrical and mechanicalbonding of the carrier 110 and flip chip 100 is shown. Anisotropicallyconductive layer 50, 60, 70 (previously bonded onto carrier 110) isbonded on its other side to the partially 30 processed HBT chip 100,flipped upside down, using the methods previously described withreference to FIGS. 7A-7B, 8A-8B, forming the structure shown in FIG. 12.At this stage, each contact electrode 113 of the carrier 110, iselectrically connected to a respective one of the contact electrodes105, 1011 of the flip chip 100. As shown in FIG. 12, each contactelectrode 113 of the carrier 110 is electrically, connected to thecontact electrode 105, 1011 of the partially processed HBT flip chippositioned directly above the respective carrier contact electrode 111.Again, it will be appreciated that precise alignment of the carrier 110and flip chip is not necessary because the surface of the electricalcontact terminals or pads 102, 111, will usually be contacted by morethan 10,000 metal pins, thus ensuring electrical connection between thecarrier 110 and flip chip 100 despite some misalignment between the two.

[0057] Once the carrier and flip chip have been electrically andmechanically bonded using the anisotropically conductive layer, furtherprocessing of the backside of flip chip 100 may take place to form acompleted HBT 130 as shown in FIG. 13. In the exemplary embodiment, thefurther processing includes selective etching away the entire InPsubstrate 109, etching the collector layer 104 and the collector contactlayer 103 to form a collector mesa structure that rises above the baselayer 106, forming a Si₃N₄ passivation layer 134 covering the base layer106 and the collector mesa, forming a contact window in the Si₃N₄ layerabove the collector mesa, forming a collector contact electrode 131 inthe contact window by making ohmic contact between the collector contactlayer 108 and a deposited metal layer patterned by conventionalphotolithography and etching, covering the back side of the HBT with alayer of polyamide 132, forming a hole extending from the top surface ofthe polyamide layer 132 to the collector contact electrode 131 usingphotolithography and etching, and filling the hole with metal forming acontact pad over the hole by electroplating of the collector contactelectrode through the hole. These steps are all familiar to one ofordinary skill in the art.

[0058] The foregoing merely illustrates the principles of the inventionin exemplary embodiments. Various modifications and alterations to thedescribed embodiments will be apparent to those skilled in the art inview of the teachings herein. For example, the pin density of theanisotropically conductive layer might be varied to produce regions withfew pins so as to not interfere with any surface elements of a circuithaving non-planar structure. Additionally, the surface of a circuithaving non-planar structure may be coated with a hard protective layerto protect it from the possibility of damage caused by the pins of theanisotropic conducive layer. As another example, it may be desirable tointroduce structural elements similar to the described electricalcontact terminals or pads on a circuit containing structure where thenumber of electrical contact terminals or pads is low. These introducedstructural elements would enhance and more fully distribute themechanical bonding and support provided by the pins but would notprovide electrical connection between the circuit containing structures.It will thus be fully appreciated that those skilled in the art will beable to devise numerous systems and methods which, although notexplicitly shown or described, embody the principles of the inventionand thus are within the spirit and scope of the invention as defined inthe appended claims.

1. An anisotropically conductive bonding interface for mechanical andelectrical bonding of a first electronic device conitainincg structure,having a respective bonding surface with at least one electricallyisolated conductive first contact pad adjacent thereto, to a secondelectronic device containing structure having a respective bondingsurface with at least one electrically isolated conductive secondcontact pad adjacent thereto, comprising: (a) a rigid insulatingsubstrate having a first and second planar surface, said first planarsurface being parallel to said second planar surface; and (b) aplurality of rigid electrically conductive pins embedded in saidinsulating substrate wherein: said plurality of pins are alignedsubstantially normal to said first and second planar surfaces, each ofsaid plurality of pins extends beyond said first and second planarsurfaces, said plurality of pins are electrically insulated from oneanother; said plurality of pins are distributed throughout saidinsulating substrate so that when said bonding interface is bonded torespective bonding surfaces of said first and second circuit containingstructures at respective ends of the pins, each one of the at least onefirst contact pad overlapping a particular one of the at least onesecond contact pads is electrically connected to said particular one ofthe at least one second contact pads by a respective group of at leastone of said pins, and said plurality of pins providing mechanicalsupport to the respective bonding surfaces of the first and seconddevice containing structures.
 2. The anisotropically conductive bondinginterface of claim 1, wherein the diameter of the portion of each ofsaid plurality of pins extending beyond said first planar surface islarger than the diameter of the portion of each of said plurality ofpins not extending beyond said first and second planar surfaces.
 3. Theanisotropically conductive bonding interface of claim 1, wherein thediameter of the portion of each of said third subset of pins extendingbeyond said first planar surface is larger than the diameter of theportion of each of said first and second subset of pins not extendingbeyond said first planar surface.
 4. The anisotropically conductivebonding interface of claim 1, wherein the diameter of the portion ofeach of said plurality of pins not extending beyond said first andsecond planar surfaces is substantially between 0.01 μm and 0.4 μm. 5.The anisotropically conductive bonding interface of claim 1, whereinsaid at least one first contact pad and said at least one second contactpad protrude from respective bonding surfaces and wherein each of saidplurality of pins extends beyond said first and second planar surfacesby a distance greater than or equal to the distance said at least onefirst contact pad and said at least one second contact pad protrude fromsaid respective bonding surfaces.
 6. The amisotropically conductivebonding interface of claim 1, wherein said plurality of pins aresubstantially evenly distributed throughout said insulating substrate.7. The anisotropically conductive bonding interface of claim 6, whereinthe average distance between said pins is substantially equal to or lessthan the thickness of said first electronic device containing structureafter the respective bonding surfaces of the first and second electronicdevice containing structures are bonded to the bonding interface andafter any subsequent processing on said first electronic circuitcontaining substrate.
 8. The anisotropically conductive bondinginterface of claim 1, wherein each of said plurality of pins extendsbeyond said first planar surface by a distance substantially the same asthe average distance between adjacent ones of said plurality of pins. 9.The anisotropically conductive bonding interface of claim 1, whereinsaid rigid insulating substrate is comprised of material selected fromthe group consisting of: SiO₂, SiNx, mica, polycarbonate, SiC andalumina.
 10. The anisotropically conductive bonding interface of claim1, wherein the distance between said first and second planar surfaces ofsaid rigid insulating substrate is substantially between 5 μm and 25 μm.11. A method for electrically and mechanically bonding a firstelectronic device containing structure having a first bonding surfacewith at least one electrically isolated conductive first contact padadjacent thereto to a second electronic device containing structurehaving a second bonding surface with at least one electrically isolatedconductive second contact pad adjacent thereto, comprising: (a)providing a rigid insulating substrate with a first and second planarsurface, said first planar surface being parallel to said second planarsurface; (b) embedding a plurality of rigid electrically conductive pinsin said insulating substrate aligned substantially normal to said firstand second planar surfaces, wherein each of said plurality of pinsextends beyond said first and second planar surfaces, said plurality ofpins being electrically insulated from one another; and (c) bonding saidfirst and second bonding surfaces to opposite ends of the plurality ofpins, wherein each one of the at least one first contact pad overlappinga particular one of the at least one second contact pad is electricallyconnected to said particular one of the at least one second contact padby a respective group of at least one pin.
 12. The method of claim 11,wherein said at least one first contact pad protrudes from the firstbonding surface and said at least one second contact pad protrudes fromthe second bonding surface.
 13. The method of claim 12, wviierein saidbonding step (c) comprises soldering a respective group of at least onepin to each overlapping region of each one of the at least one firstcontact pad overlapping a particular one of the at least one secondcontact pad, and soldering a respective group of at least one pin toeach overlapping region of each one of the at least one second contactpad overlapping a particular one of the at least one first contact pad.14. The method of claim 12, wherein said bonding step (c) comprisescausing at least a part of the portion of each of a respective group ofat least one pin that extends beyond said first planar surface topenetrate each overlapping region of each one of the at least one firstcontact pad overlapping a particular one of the at least one secondcontact pad, and causing at least a part of the portion of each of arespective group of at least one pin that extends beyond said secondplanar surface to penetrate each overlapping region of each one of theat least one second contact pad overlapping a particular one of the atleast one of the first contact pad.
 15. The method of claim 12, furthercomprising before said bonding step (c), coating the first and secondbonding surfaces, except for the at least one first contact pad and theat least one second contact pad, with a relatively soft insulatingmaterial having thickness substantially equal to a distance that the atleast one first contact pad protrudes from the first bonding surface anda distance that the at least one second contact pad protrudes from thesecond bonding surface, wherein said bonding step comprises causing atleast a part of each of a respective group of at least one pin thatextends beyond the first planar surface to penetrate each overlappingregion of each one of the at least one first contact pad overlapping aparticular one of the at least one second contact pad, and causing atleast a part of the portion of each of a respective group of a least onepin that extends beyond the second planar surface to penetrate eachoverlapping region of each one of the at least one second contact padoverlapping a particular one of the at least one of the first contactpad, and for each pin that does not penetrate the at least one firstcontact pad or the at least one second pad, causing at least parts ofrespective portions that extend beyond the first and second planarsurfaces to penetrate the relatively soft insulating material on thefirst andd second bonding surfaces.
 16. A method of making asemiconductor device, the method comprising: (a) providing asemiconductor substrate having a plurality of semiconductor layersformed thereon, (b) forming at least one first electrical contactterminal on at least one of said semiconductor layers; (c) providing anelectronic circuit containing carrier having an interface surface withat least one second electrical contact terminal adjacent thereto; (d)providing a rigid insulating substrate with a first and second planarsurface, said first planar surface being parallel to said second planarsurface; and (e) embedding a plurality of electrically conductive pinsin said insulating substrate aligned substantially normal to said firstand second planar surfaces, wherein each of said plurality of pinsextends beyond said first and second planar surfaces by a fixed amount,said plurality of pins being electrically insulated from one another;(f) bonding the at least one first electrical contact terminal on the atleast one of said semiconductor layers to first ends of a respectivefirst group of pins; (g) bonding the at least one second electricalcontact terminal to the second ends of a respective second group ofpins, each respective first group of pins having at least one pin incommon with each respective second group of pins so as to electricallyconnect each one of the at least one first electrical contact terminalwith a respective one of the at least one second electrical contactterminal; and (h) after said bonding steps (f) and (g), carrying out asequence of processing steps on said semiconductor substrate having theplurality of semiconductor layers formed thereon, and forming at leastone third electrical contact terminal facing away from the pins.
 17. Themethod of claim 16, wherein said semiconductor device is a high-speedheterojunction bipolar transistor.